The present disclosure relates to a semiconductor storage device with a transistor having a fin structure.
Recently, it has been proposed to utilize transistors with a fin structure (hereinafter referred to as a “fin transistor”) in the field of semiconductor devices. FIG. 7 schematically illustrates a fin transistor. Unlike a metal oxide semiconductor (MOS) transistor having a two-dimensional structure, its source and drain have a raised, three-dimensional structure called “fin.” Its gate is disposed so as to wrap around a channel region defined between the source and drain in this fin.
In this fin structure, the channel region is defined by three surfaces of the fin, thereby improving channel controllability significantly compared to conventional ones. As a result, various advantages, including reducing the leakage power, increasing the ON-state current, and lowering the operating voltage, are achieved. This leads to improving the performance of the semiconductor integrated circuit.
Japanese Unexamined Patent Publication No. 2006-323950 discloses a semiconductor storage device in which a cross-coupled circuit is provided between two bit lines that form a bit line pair. Japanese Unexamined Patent Publication No. 2002-93174 discloses an example of a sense amplifier circuit provided in a memory.